Code Size Efficiency in Global Scheduling for VLIW/EPIC Style Embedded Processors

In embedded computing, code size is very important for system cost and performance. In global scheduling for VLIW/EPIC style embedded processors, region-enlarging optimizations, especially tail duplication, are commonly used to exploit instruction level parallelism (ILP) to boost the performance. The code size increase due to such optimizations, however, raises serious concerns about the affected I-cache, branch and TLB performance. In this paper, we focus on the code size efficiency of code size related optimizations in global scheduling. First, we propose to use the ratio of static IPC (instruction per cycle) changes to code size changes as a quantitative measure of the code size efficiency at compile time for any code size related optimization. Then, based on the code size efficiency of tail duplication, we propose the solutions to the two related problems: (1) how to achieve the best performance for a given code size increase, (2) how to get the optimal code size efficiency for any program. Our study shows that code size increase resulting from tail duplication has a significant but varying impact on IPC, e.g., the first 2% code size increase results in 18.5% increase in static IPC, while the static IPC changes less than 1% when given code size increase ranging from 20% to 30%. We then use this feature to define the optimal code size efficiency and to derive a simple, yet robust threshold scheme finding it. The experimental results using SPECint95 benchmarks show that this threshold scheme finds the optimal efficiency accurately. While the optimal efficiency results show an average increase of 2% in code size over original code size, the improved I-cache performance (4% decrease in I-cache penalty for a 32KB I-cache) is observed due to the increased locality. Overall, the optimal efficiency results show a speedup of 17% over the natural treegion (treegion without any tail duplication) results. The experiment with different I-cache sizes shows that the speedup also holds for a small I-cache of 16KB. 1 This is an expanded version of a paper presented at the INTERACT-6 workshop in conjunction with HPCA-8 on February 3, 2002. Approximately one third of this paper is new and never before published.